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preliminary this document contains in f o r mation on a product under d e v elopment at ad v anced micro d e vice s . the in f o r mation is intended to help y ou e v aluate this product . amd rese r v es the r ight to change or discontinue wo r k on this proposed product without notic e . pu b lication# 17306 r e v : b amendment/ 0 issue date : ja nuary 199 9 1- 71 AM79C981 integrated multipo r t repeater plus (imr+) distinctive char a cteristics n enhanced ve r sion of amd s am79c980 integrated multipo r t repeater (imr) chip with the f oll o wing enhancements: additional management po r t f eatures mini m um mode pr o vides suppo r t f or an e xtra f our led outputs per po r t f or additional status in non-intelligent repeater designs pin/so c k et-compati b le with the am79c980 imr chip fully ba c k w ard-compati b le with e xisting imr d e vice designs n interfaces direct l y with the am79c987 himib d e vice to b uild a ful l y managed m ultipo r t repeater n cmos d e vice features high integration and l o w p o wer with a single + 5 v supp l y n repeater functions comp l y with ieee 802.3 repeater unit speci?ations n eight integral 10 b ase-t transceive r s utilize the required predisto r tion transmission technique n attachment unit interface ( a ui) po r t all o ws connectivity with 10 b ase-5 (ethernet) and 10 b ase-2 (cheapernet) net w orks , as well as 10 b ase-f and/or fiber optic inte r -repeater link (foirl) segments n on-boa r d pll , manchester encoder/decode r , and fifo n expandable to increase number of repeater po r ts n all po r ts can be separate l y isolated (pa r titioned) in response to e xcessive collision conditions or fault conditions n net w ork management and optional features are accessible th r ough a dedicated serial management po r t n t wisted-pair lin k t est capability con f orming to the 10 b ase-t standa r d . the receive lin k t est function can be optional l y disabled th r ough the management po r t to facilitate inte r operability with d e vices that do not implement the lin k t est function n p r ogrammable option of a utomatic p olarity detection and correction permits automatic rec o very due to wiring er r o r s n full amplitude and timing regeneration f or retransmitted w a ve f orms n preamble loss effects eliminated b y deep fifo general description the integrated multipo r t repeater plus (imr+) chip is a vlsi circuit that pr o vides a system-l e v el solution to de- signing a compliant 802.3 repeater inco r porating 10base - t transcei v er s . the d e vice integrates the repeater functions speci ed b y section 9 of the ieee 802.3 standard an d t wisted- p ai r t ranscei v er functions complying with the 10base-t standard . the AM79C981 pr o vides eight integral twisted-pair medium attachment units (m a us) and an attachment unit inter f ace ( a ui) po r t in an 84-pin plastic leaded chip car r ier (plcc). a net w o r k based on the 10base-t standard uses un- shielded twisted-pair ca b le s , there b y pr o viding an eco- nomical solution to net w o r king b y all o wing the use of l o w-cost unshielded twisted-pair (utp) ca b le or e xisting telephone wi r ing . the total number of po r ts per repeater unit can be in- creased b y connecting multiple imr+ d e vices through their e xpansion po r t s , minimizing the total cost per re- peater po r t . fu r the r mor e , a general-pu r pose attach- ment unit inter f ace ( a ui) pr o vides connection capability to 10base-5 (ethe r net) and 10base-2 (cheape r net) coaxial net w o r k s , as well as 10base-f and/or fiber optic inter-repeater link (foirl) ?er segment s . net- w o r k management and test functions are pr o vided throug h ttl-compati b le i/o pin s . the imr+ d e vice inter f aces directly with amd s am79c987 hard w are implemented management in- f o r mation base (himib) chip to b uild a fully managed m ultipo r t repeater as speci?d b y the ieee 802.3 (l a y er management f or 10 mb/s baseband repeaters) standard . when the imr+ and himib d e vices are interconnected, complete repeater and per-po r t statis- tics are maintained and can be accessed on demand using a simple 8-bit parallel inter f ac e .
amd preliminary 1 C 72 AM79C981 for application examples on building a fully managed repeater using the imr+ and himib devices, refer to amds ieee 802.3 repeater technical manual (pid# 17314a) and the isa-hub tm user manual (pid # 17642a). the device is fabricated in cmos technology and re- quires a single +5 v supply. block diagram rx mux phase = lock ed loop fifo fifo c o nt rol preamble jam sequence manchester encoder imr+ chip control partitioning link test timers manchester decoder aui port di ci do tp port 0 rxd txd txp tp port 7 rxd txd txp reset clock gen x 1 x 2 expansion port req ack col dat jam test and management port si so rst sclk test crs str tx mux 17306b-1 related amd products part no. description am79c98 twisted pair ethernet transceiver (tpex) am79c100 twisted pair ethernet transceiver plus (tpex+) am7996 ieee 802.3/ethernet/cheapernet transceiver am79c987 hardware implemented management information base ? (himib ? ) am79c940 media access controller for ethernet (mace ? ) am7990 local area network controller for ethernet (lance) am79c90 cmos local area network controller for ethernet (c-lance) am79c900 integrated local area communications controller ? (ilac c ? ) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa + single-chip ethernet controller for isa (with microsoft a plug n play a support) am79c965 pcnet-32 single-chip 32-bit ethernet controller am79c970 pcnet-pci single-chip ethernet controller (for pci bus) am79c974 pcnet-scsi combination ethernet and scsi controller for pci systems
AM79C981 1C 73 preliminary connection di a gram plcc dv dd 1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 3 3 4 3 5 36 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 37 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 84 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 rxd0+ txd6+ txd6 txp6+ txp6 txd4 txd4+ txp4+ txp4 txd0+ txd0 txp1+ txp1 txd2+ txd2 txp2+ txp2 rxd0 rxd2+ rxd4+ rxd6+ rxd2 rxd4 rxd6 rxd7+ rxd7 txd7+ txd7 dv ss txp7 txp7+ dv dd txd5 txp5+ txp5 txd5+ dv ss txp3 so dv ss str dv dd crs si sclk test rst dv ss x 1 x 2 ack col jam dat req dv ss dv dd dv ss do do+ dv ss dv dd txd1+ txd1 txp1+ txp1 txd3+ txd3 txp3+ dv dd dv ss ci+ ci di+ di av ss rxd1+ rxd1 rdx3+ rxd3 av dd rxd5+ rxd5 imr+ chip AM79C981 17306 b -2
amd preliminary 1 C 74 AM79C981 logic symbol do+ doC di+ diC ci+ ciC sclk x1 test rst dv ss av ss str crs jam dat txd+ txp+ txdC txpC rxd+ rxdC dv dd av dd AM79C981 aui twisted pair ports (8 ports) si so ack col req expansion port port activity monitor management port 17306b-3 x2 logic diagram aui management port expansion port twisted pair port 0 twisted pair port 7 17306b-4 repeater state machine
AM79C981 1C 75 preliminary ordering inform a tion standa r d p r oducts amd standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . the order number ( v alid combination) is f o r med b y a combination of the elements bel o w . v alid combinations v alid combinations list congurations planned to be sup- po r ted in v olume f or this d e vic e . consult the local amd sales of ce to con r m a v ailability of specic v alid combinations and to che c k on n e wly released combination s . AM79C981 j c device number/description AM79C981 integrated multiport repeater plus (imr+) optional p r ocessing blank = standard processing oper a ting conditions c = commercial ( 0 c to +7 0 c) p a ck a g e type j = 84- pin plastic leaded chip carrier (pl 084) speed not applica b le v alid combinations AM79C981 jc
1C 76 AM79C981 preliminary pin description a ck a c kn o wledge input , active l o w when this input is asse r ted, it signals to the requesting imr+ d e vice that it m a y control the d a t and j am pin s . if the imr+ chip is not requesting control of the d a t line ( req pin high), then the asse r tion of the a ck signal indicates the presence of v alid collision status on the j am or v alid data on the d a t lin e . a v dd analog p o wer p o wer pin these pins supply the + 5 v to the rxd+/?recei v er s , the di+/?and ci+/?recei v er s , the do+/?d r i v er s , the inte r nal pll, and the inte r nal v oltage re f erence of the imr+ d e vic e . these p o w er pins should be decoupled and k ept separate from other p o wer and g round plane s . a v ss analog g r ound g r ound pin these pins are the 0 v re f erence f or a v dd . col expansion collision input , active l o w when this input is asse r ted b y an e xte r nal arbite r , it sig- ni es that more than one imr+ d e vice is acti v e and that each imr+ d e vice should gene r ate the collision j am sequence independentl y . ci+ , ci cont r ol in input a ui po r t dif f erential recei v e r . signals comply with ieee 802.3, section 7. crs carrier sense output the states of the inte r nal car r ier sense signals f or the a ui po r t and the eight twisted-pair po r ts are se r ially output on this pin conti n uousl y . the output se r ial bit stream is synchroni z ed to the x 1 clo c k. d a t data input/output/3- state in non-collision condition s , the acti v e imr+ d e vice will dri v e d a t with nrz data, including regene r ated pre- am b l e . du r ing collision, when j am = high, d a t is used to signal a m ultipo r t ( d a t = 0) or single-po r t ( d a t = 1) condition. whe n a ck is not asse r ted, d a t is in high impedanc e . i f req and a ck are both asse r ted, then d a t is an out- put . if a ck is asse r ted and req not asse r ted, then d a t is an input. this pin needs to be either pulled up or pulled d o wn through a high- v alue resisto r . di+ , di data in input a ui po r t dif f erential recei v e r . signals comply with ieee 802.3, section 7. do+ , do data out output a ui po r t dif f erential d r i v e r . signals comply with ieee 802.3, section 7. d v dd digital p o wer p o wer pin these pins supply + 5 v to the logic po r tions of the imr+ chip and th e txp+/ , txd+/? and do+/?line d r i v er s . d v ss digital g r ound g r ound pin these pins are the 0 v re f erence f or d v dd . j am jam input/output/3- state when j am is asse r ted, the state of d a t will indicate either a m ultipo r t ( d a t = 0) or single-po r t ( d a t = 1) col- lision condition. when a ck is not asse r ted, j am is in high impedanc e . i f req and a ck are both asse r ted, then j am is an out- put . if a ck is asse r ted and req not asse r ted, then j am is an input. this pin needs to be either pulled up or pulled d o wn through a high- v alue resisto r . d v dd pin # d v ss pin # function 19 16 tp po r ts 0 & 1 d r i v ers 28 31 tp po r ts 2 & 3 d r i v ers 43, 49 35, 37, 46, 51 core logic and e xpansion and control pins 59 56 tp po r ts 4 & 5 d r i v ers 68 71 tp po r ts 6 & 7 d r i v ers
AM79C981 1C 77 preliminary req request output , active l o w this pin is d r i v en l o w when the imr+ chip is acti v e . an imr+ chip is acti v e when it has one or more po r ts receiving or colliding or is in the state where it is still tr ansmitting data from the inte r nal fif o . the asse r tion of this signal signies that the imr+ d e vice is request- ing the use of the d a t and j am lines f or the trans f er of repeated data or collision status to other imr+ d e vice s . rst reset input , active l o w dr iving this pin l o w resets the inte r nal logic of the imr+ d e vic e . reset should be synchroni z ed to the x 1 clo c k if either e xpansion or po r t activity monitor is used. rxd+ 0? , rxd 0? receive data input 10base- t po r t dif f erential recei v e inputs (8 po r ts). sclk serial clo c k input in no r mal operating mod e , se r ial data (input or output) is clo c k ed (in or out) on the r ising edge of the signal on this pin . sclk is asynchronous to x 1 and can ope r ate up to 10 mhz . in minimum mod e , this pin, together with the si pin, controls which in f o r mation is output on the so pin. si serial in input in no r mal ope r ating mod e , the si pin is used f or test/ management se r ial input po r t . management com- mands are clo c k ed in on this pin synchronous to the sclk input . in mini m um mod e , this pin, together with the sclk pin, controls which in f o r mation is output on the so pin. in minimum mod e , the state of si at the deasse r tion of rst signal dete r mines the programming of automatic pola r ity detection/correction f or 10base- t po r t s . so serial out output in no r mal operating mod e , the so pin is used f or test/ management serial output po r t . management results are clo c k ed out on this pin synchronous to the sclk input . in mini m um mod e , the so pin is used to se r ially output the v a r ious status in f o r mation based on the state of the si and sclk pin s . str store input/output as an output, this pin goes high f or t w o x 1 clo c k cycle times after the nine car r ier sense bits are output on the crs pin . note that the carrier sense signals arriving from each po r t are latched inte r nall y , so that an acti v e tr ansition is remembered bet w een sample s . the accu- r acy of the car r ier sense signals produced in this man- ner is 10 bit times (1 m s). when used in conjunction with the himib d e vic e , the str pin will be con gured as an input automatically after a hard w are reset . the himib d e vice uses this input to com m unicate with the imr+ d e vic e . when used with the himib chi p , this pin must be pulled up via a high- v alue resisto r . test t est pin input , active high this pin should be tied l o w f or no r mal ope r ation . if this pin is d r i v en high, then the imr+ d e vice can be pro g r ammed f or loopba c k t est mod e . als o , if this pin is high when the rst pin is deasse r ted, the imr+ de- vice will enter the minimum mod e . an i n v e r ted v ersion of the rst signal can be used to pro g ram the d e vice into the minimum mod e . sclk si so output 0 0 tp p o r ts recei v e p ola r ity status + a ui sq e t est error status 0 1 bit rate error (all po r ts) 1 0 tp p o r ts link status + a ui loopba c k status 1 1 p o r t p a r titioning status (all po r ts) t est si functions 0 0 no r mal management mode 0 1 no r mal management mode 1 0 minimum mod e , recei v e p ola r ity correction disa b led 1 1 minimum mod e , recei v e p ola r ity correction ena b led
1C 78 AM79C981 preliminary txd+ 0? , txd 0? t ransmit data output 10base- t po r t dif f erential d r i v ers (8 po r ts). txp+ 0? , txp 0? t ransmit predisto r tion output 10base - t transmit w a v e f o r m predisto r tion control dif f erential outputs (8 po r ts). x 1 c r ystal 1 c r ystal connection the inte r nal clo c k gene r ator uses a 20 mhz c r ystal at- tached to pins x 1 and x 2 . alte r nati v el y , an e xte r nal 2 0 mhz cmos clo c k signal can be used to d r i v e this pin. x 2 c r ystal 2 c r ystal connection the inte r nal clo c k gene r ator uses a 20 mhz c r ystal at- tached to pins x 1 and x 2 . if an e xte r nal clo c k source is used, this pin should be left unconnected.
amd preliminary 1 C 7 9 AM79C981 functional description the AM79C981 integrated multiport repeater plus de- vice is a single chip implementation of an ieee 802.3/ethernet repeater (or hub). in addition to the eight integral 10base-t ports plus one aui port comprising the basic repeater, the imr+ chip also provides the hooks necessary for complex network management and diagnostics. the imr+ device is also expandable, enabling the implementation of high port count repeat- ers based on several imr+ devices. the imr + device interfaces directly with amds am79c987 hardware implemented management infor- mation base (himib) device to allow a fully managed multiport repeater to be implemented as specified by the layer management for 10 mb/s baseband repeaters standard. when the imr+ and himib devices are used as a chip set, the himib device maintains complete re- peater and per port statistics which can be accessed on demand by a microprocessor through a simple 8-bit par- allel port. the imr+ chip complies with the full set of repeater ba- sic functions as defined in section 9 of iso 8802.3 (ansi/ieee 802.3c). these functions are summarized below. repeater function if any single network port senses the start of a valid packet on its receive lines, then the imr+ device will re- transmit the received data to all other enabled network ports. the repeated data will also be presented on the dat line to facilitate multiple-imr+ device repeater applications. signal regeneration when re-transmitting a packet, the imr+ device en- sures that the outgoing packet complies with the 802.3 specification in terms of preamble structure, voltage am- plitude, and timing characteristics. specifically, data packets repeated by the imr+ chip will contain a mini- mum of 56 preamble bits before the start of frame de- limiter. in addition, the voltage amplitude of the repeated packet waveform will be restored to levels specified in the 802.3 specification. finally, signal symmetry is re- stored to data packets repeated by the imr+ device, removing jitter and distortion caused by the network cabling. jabber lockup protection the imr+ chip implements a built-in jabber protection scheme to ensure that the network is not disabled due to transmission of excessively long data packets. this pro- tection scheme will automatically interrupt the transmit- ter circuits of the imr+ device for 96-bit times if the imr+ device has been transmitting continuously for more than 65,536-bit times. this is referred to as mau jabber lockup protection (mjlp). the mjlp status for the imr+ chip can be read through the management port using the get mjlp status command (m bit returned). collisio n handling the imr+ chip will detect and respond to collision condi- tions as specified in 802.3. a multiple-imr+ device re- peater implementation also complies with the 802.3 specification due to the inter-imr+ chip status commu- nication provided by the expansion port. specifically, a repeater based on one or more imr+ devices will han- dle the transmit collision and one-port-left collision con- ditions correctly as specified in section 9 of the 802.3 specification. fragment extension if the total packet length received by the imr+ device is less than 96 bits, including preamble, the imr+ chip will extend the repeated packet length to 96 bits by append- ing a jam sequence to the original fragment. auto partitioning/reconnection any of the integral tp ports and aui port can be parti- tioned under excessive duration or frequency of colli- sion conditions. once partitioned, the imr+ device will continue to transmit data packets to a partitioned port, but will not respond (as a repeater) to activity on the par- titioned ports receiver. the imr+ chip will monitor the port and reconnect it once certain criteria indicating port wellness are met. the criteria for reconnection are specified by the 802.3 standard. in addition to the stan- dard reconnection algorithm, the imr+ device imple- ments an alternative reconnection algorithm which provides a more robust partitioning function for the tp ports and/or the aui port. each tp port and the aui port are partitioned and/or reconnected separately and inde- pendently of other network ports. either one of the following conditions occuring on any enabled imr+ device network port will cause the port to partition: a . a collision condition exists continuously for a time between 1024- to 2048-bit times (aui portsqe signal active; tp portsimultaneous transmit and receive) b . a collision condition occurs during each of 32 con- secutive attempts to transmit to that port. once a network port is partitioned, the imr+ device will reconnect that port if the following is met: a . standard reconnection algorithma data packet longer than 512-bit times (nominal) is transmitted or received by the partitioned port without a collision. b . alternate reconnection algorithma data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision.
amd preliminary 1 C 8 0 AM79C981 the reconnection algorithm option (standard or alter- nate) is a global function for the tp ports, i.e. all tp ports use the same reconnection algorithm. the aui reconnection algorithm option is programmed inde- pendently of the tp port reconnection option. link test the integral tp ports implement the link test function as specified in the 802.3 10base-t standard. the imr+ device will transmit link test pulses to any tp port after that ports transmitter has been inactive for more than 8 to 17 ms. conversely, if a tp port does not receive any data packets or link test pulses for more than 65 to 13 2 ms and the link test function is enabled for that port then that port will enter link fail state. a port in link fail state will be disabled by the imr+ chip (repeater transmit and receive functions disabled) until it receives either four consecutive link test pulses or a data pack- et. the link test receive function itself can be disabled via the imr+ chip management port on a port-by-port basis to allow the imr+ device to interoperate with pre- 10base-t twisted pair networks that do not implement the link test function. this interoperability is possible because the imr+ device will not allow the tp port to en- ter link fail state, even if no link test pulses or data packets are being received. note however that the imr+ chip will always transmit link test pulses to all tp ports regardless of whether or not the port is enabled, partitioned, in link fail state, or has its link test receive function disabled. polarity reversal the tp ports have the optional (programmable) ability to invert (correct) the polarity of the received data if the tp port senses that the received data packet waveform polarity is reversed due to a wiring error. this receive circuitry polarity correction allows subsequent packets to be repeated with correct polarity. this function is exe- cuted once following reset or link fail, and has a programmable enable/disable option on a port-by-port basis. this function is disabled upon reset and can be enabled via the imr+ chip management port. reset the imr+ device enters reset state when the rst pin is driven low. after the initial application of power, the rst pin must be held low for a minimum of 150 m s (3000 x1 clock cycles). if the rst pin is subsequently asserted while power is maintained to the imr+ device, a reset duration of only 4 m s is required. the imr+ chip continues to be in the reset state for 10 x1 clocks (0. 5 m s) following the rising edge of rst . during reset, the output signals are placed in their inactive states. this means that all analog signals are placed in their idle states, bidirectional signals (except str signal) are not driven, active low signals are driven high, and all ac- tive high signals and the str pin are driven low. an internal circuit ensures that a minimum reset pulse is generated for all internal circuits. for a rst input with a slow rising edge, the input buffer threshold may be crossed several times due to ripple on the input waveform. in a multiple imr+ chip repeater the rst signal should be applied simultaneously to all imr+ devices and should be synchronized to the external x1 clock. reset synchronization is also required when accessing the pam (port activity monitor). the si signal should be held high for at least 500 ns fol- lowing the rising edge of rst . table 1 summarizes the state of the imr+ chip following reset. table 1. imr+ chip after reset function state after reset pull up/pull down active low outputs high no active high outputs low no so output high no dat, jam hi-impedance either str low pull up* transmitters (tp and aui) idle no receivers (tp and aui) enabled terminated aui partitioning/reconnection algorithm standar d algorithm n/a tp port partitioning/reconnection algorithm standard algorithm n/a link test function for tp ports enabled, tp ports in link fail n/a automatic receiver polarity reversal function disabled n/a *only when used with the himib device.
amd preliminary 1 C 81 AM79C981 expansion port the imr+ chip expansion port is comprised of five pins; two are bi-directional signals (dat and jam), two are in- put signals ( ack and col ), and one is an output signal ( req ). these signals are used when a multiple-imr+ device repeater application is employed. in this configu- ration, all imr+ chips must be clocked synchronously with a common clock connected to the x1 inputs of all imr+ devices. reset needs to be synchronized to x1 clock. the imr+ device expansion scheme allows the use of multiple imr+ chips in a single board repeater or a modular multiport repeater with a backplane architec- ture. the dat pin is a bidirectional i/o pin which can be used to transfer data between the imr+ devices in a multiple-imr+ chip design. the data sent over the dat line is in nrz format and is synchronized to the common clock. the jam pin is another bidirectional i/o pin that is used by the active imr+ chip to communicate its internal status to the remaining (inactive) imr+ devices. when jam is asserted high, it indicates that the active imr+ device has detected a collision condition and is generat- ing jam sequence. during this time when jam is as- serted high, the dat line is used to indicate whether the active imr+ chip is detecting collision on one port only or on more than one port. when dat is driven high by the imr+ chip (while jam is asserted by the imr+ chip), then the active imr+ device is detecting a collision condition on one port only. this one-port-left signaling is necessary for a multiple-imr+ device re- peater to function correctly as a single multiport repeater unit. the imr+ chip also signals the one port left colli- sion condition in the event of a runt packet or collision fragment; this signal will continue for one expansion port bus cycle (100 ns) before deasserting req . the arbitration for access to the bussed bi-directional signals (dat and jam) is provided by one output ( req ) and two inputs ( ack and col ). the imr+ chip asserts th e req pin to indicate that it is active and wishes to drive the dat and jam pins. an external arbiter senses th e req lines from all the imr+ devices and asserts the ack line when one and only one imr+ chip is asserting it s req line. if more than one imr+ chip is asserting its req line, the arbiter must assert the col signal, indi- cating that more than one imr+ device is active. more than one active imr+ device at a time constitutes a colli- sion condition, and all imr+ devices are notified of this occurence via the col line of the expansion port. note that a transition from multiple imr+ devices arbi- trating for the dat and jam pins (with col asserted, ack deasserted) to a condition when only one imr+ chip is arbitrating for the dat and jam pins (with ack asserted , col deasserted) involves one expansion port bus cycle (100 ns). during this transitional bus cycle, col is deasserted, ack is asserted, and the dat and jam pins are not driven. however, each imr+ device will remain in the collision state (transmitting jam se- quence) during this transitional bus cycle. in subse- quent expansion port bus cycles ( req and ack still asserted), the imr+ devices will return to the master and slaves condition where only one imr+ device is ac- tive (with collision) and is driving the dat and jam pins. an understanding of this sequence is crucial if non- imr+ devices (such as an ethernet controller) are con- nected to the expansion bus. specifically, the last device to back off of the expansion port after a multi- imr+ chip collision must assert the jam line until it too drops its request for the expansion port. external arbiter a simple arbitration scheme is required when multiple imr+ devices are connected together to increase the to- tal number of repeater ports. the arbiter should have one input ( req1 ... reqn ) for each of the n imr+ de- vices to be used, and two global outputs ( col and ack ). this function is easily implemented in a pal de- vice, with the following logic equations: ac k = req1 & req2 & req3 & .... reqn + req1 & req2 & req3 & .... reqn + req1 & req2 & req3 & .... reqn co l = ack & (req1 + req2 + req3 + ... reqn) above equations are in positive logic, i.e., a variable is true when asserted. a single palce16v8 will perform the arbitration func- tion for a repeater based on several imr+ devices.
amd preliminary 1 C 82 AM79C981 arbiter AM79C981 imr+ chip 1 ack col rst x1 ack col rst x1 dat jam req dat jam ack col rst x1 dat jam d ff ck q d xtal osc. async reset 1/2 74 col ack ack req req req AM79C981 imr+ chip 2 AM79C981 imr+ chip 3 bus transceivers needed if dat and jam buses exceed 100 pf loading. ab dir note 1 note 1: direction dir b ? a low a ? b high 17306b-5 req 2 req 3 req1 figure 1. multiple imr+ devices modular repeater design the expansion port of the imr+ chip also allows for modular expansion. by sharing the arbitration duties be- tween a backplane bus architecture and several sepa- rate repeater modules one can build an expandable repeater based on modular plug-in cards. each repeater module performs the local arbitration function for the imr+ devices on that module, and provides sig- nals to the backplane for use by a global arbiter. for more detailed information, see amds ieee 802.3 repeater technical manual, pid# 17314a.
amd preliminary 1 C 83 AM79C981 repeater mac interconnection because all repeated data in the imr+ chip or multi- imr+ chip design is available on the expansion port, all network traffic can be monitored by an external media access controller (mac) device such as the am7990, am79c900, am79c940, or am79c960. a repeater with such a controller is capable of providing extensive hub management functions, as well as being addressable as a network node. the mac device can gather statistics and data concerning the state of the hub and the network, and the network addressability allows a remote management station to monitor this statistical data and to request actions to be performed by the repeater (i.e. port enable/disable). figure 2 shows how to interface a repeater based on multiple imr+ devices to an ethernet controller such as the am79c900 ilacc or the am7990 lance. for more information on this design, refer to amds ieee 802.3 repeater technical manual, pid# 17314a. am7990 lance am79c900 ilacc am79c940 mace or am79c960 pcnet-isa imr+1 col ack dat jam req rs t x1 imr+2 rs t x1 arst reset arst done_count new96 tck 20mhz txc imr+n rs t x1 rxc rena rxd ack jam rts rts rxc sync crs rcken dat txd txd tck dat jam ack reqn req2 req1 col rts tck new96 done_count cd t cdt ackclk rtsclk xcol colclk q0 q1 q2 q3 q4 q5 q6 rtsclk ackclk tck tck data arbiter palce16v8 interface palce16v8 cdt counter palce22v10 20 mhz osc. col ack dat jam req col ack dat jam req 14396c-033a 17306b-6 figure 2. expandable modular repeater
amd preliminary 1 C 84 AM79C981 management port the imr+ device management functions are enabled when the test pin is tied low. the management com- mands are byte oriented data and are input serially on the si pin. any responses generated during execution of a management command are output serially in a byte- oriented format by the imr+ device on the so pin. both the input and output data streams are clocked with the rising edge of the sclk pin. the serial command data stream and any associated results data stream are structured in a manner similar to the rs232 serial data format, i.e., one start bit followed by eight data bits. the externally generated clock at the sclk pin can be either a free running clock synchronized to the input bit patterns or a series of individual transitions meeting the setup and hold times with respect to the input bit pattern. if the latter method is used, it is to be noted that 20 sclk clock transitions are required for proper execution of management commands that produce so data, and that 14 sclk clock transitions are needed to execute management commands that do not produce so data. management commands the following section details the operation of each man- agement command available in the imr+ chip. in all cases, the individual bits in each command byte are shown with the msb on the left and the lsb on the right. data bytes are received and transmitted lsb first and msb last. see table 2 for a summary of the manage- ment commands. sclk si so str t d0 d 1 d 2 d 3 d 4 d 5 d6 d7 command execution phase results phase str t d0 d 1 d 2 d 3 d 4 d 5 d6 d7 next command 17306b-17 management command/response timing sclk si so command execution phase next command execution phase str t d0 d 1 d 2 d 3 d 4 d 5 d6 d7 str t d0 d 1 d 2 d 3 d 4 d 5 d6 d7 17306b-18 management command timing with no response
amd preliminary 1 C 85 AM79C981 table 2. management port command summary commands si data so data set (write) opcodes imr+ chip programmable options 0000 1csa alternate aui partitioning algorithm 0001 1111 alternate tp partitioning algorithm 0001 0000 aui port disable 001 0 1111 aui port enable 001 1 1111 tp port disable 001 0 0### tp port enable 001 1 0### disable link test function (per tp port) 010 0 0### enable link test function (per tp port) 010 1 0### disable automatic receiver polarity reversal (per tp port) 011 0 0### enable automatic receiver polarity reversal (per tp port) 011 1 0### get (read) opcodes aui port status (b, s, l cleared) 100 0 111 1 pbs l 0000 tp port partitioning status 100 0 000 0 c7...c0 bit rate status of tp ports 101 0 000 0 e7...e0 link test status of tp ports 110 1 000 0 l7...l0 receive polarity status of all tp ports 111 0 000 0 p7...p0 mjlp status 111 1 000 0 m00 0 0000 versio n 111 1 111 1 xxx x 0001 aui port status (s, l cleared) 100 0 101 1 pbs l 0000 aui port status (b cleared) 100 0 110 1 pbs l 0000 aui port status (none cleared) 100 0 100 1 pbs l 0000 notes: 1. unused opcodes are reserved for future use. 2. ### is the port number (000 to 111 for tp0 to tp7)
amd preliminary 1 C 86 AM79C981 set (write) opcodes imr+ chip programmable options si data : 000 0 1csa so data: none imr+ chip programmable options can be enabled (dis- abled) by setting (resetting) the appropriate bit in the command string. the three programmable bits are: c ci reporting; s aui sqe test mask, and a alternative port activity monitor (pam) function. these options can be enabled (disabled) by setting (re- setting) the appropriate bit in the command string. when writing to this register through the am79c987 himib device, the a and c bits should not be changed (a=0, c=1). cci reporting setting this bit alters the function of the str pin. in this mode, the str pin becomes an input in response to the amds am79c987 himib device. upon deassertion of rst , the himib automatically sets this bit following imr/ imr+ device type detection. when this mode is selected, the crs output bit string format is modified to include ci carrier bit (in addition to aui carrier). this bit occupies the bit position immedi- ately preceding the aui bit in the crs bit string (10 bits) output. note that the aui bit gets asserted if either the ci or di signal pairs are active. s aui sqe test mask setting this bit allows the imr+ chip to ignore activity on the ci signal pair, in the sqe test window, following a transmission on the aui port. this event occurs when the attached mau has the sqe test option enabled, therefore generating a burst of ci activity following every transmission. this is interpreted by the imr+ device as a collision, causing the imr+ device to generate a full jam pattern. although the mau attached to a repeater is required not to have its sqe test function active, this is a common installation error, causing difficulty in diagnos- ing network throughput problems. the sqe test window, as defined by the ieee 802.3 (section 7.2.2.2.4), is from 6-bit times to 34-bit times (0. 6 m s to 3.4 m s). this includes delay introduced by a 5 0 m aui. ci activity that occurs outside this window is not ignored and is treated as true collision. note that enabling this function does not prevent the re- porting of this condition by the imr+ device and the two functions operate independently. aalternative port activity monitor (pam) function setting the alternative port activity monitor function al- lows the pam function to be altered such that the carrier sense data is presented unmodified. in default opera- tion the pam output (carrier sense bits in the crs bit stream) are masked if the port is either disabled or parti- tioned. this does not allow the repeater management software to sense activity on all segments at all times. the ability to monitor partitioned or disabled ports allows fault tolerance to be built into the repeater management software. alternate aui port partitioning algorithm si data: 00011111 so data: none the aui port partitioning/reconnection scheme can be programmed for the alternate (transmit only) reconnec- tion algorithm by invoking this command. to return the aui back to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the imr+ device. standard partitioning algorithm is se- lected upon reset. alternate tp ports partitioning algorithm si data: 00010000 so data: none the tp ports partitioning/reconnection scheme can be programmed for the alternate (transmit only) reconnection algorithm by invoking this command. all tp ports are affected as a group by this command. to return the tp ports back to the standard (transmit or re- ceive) reconnection algorithm, it is necessary to reset the imr+ device. the standard partitioning algorithm is selected upon reset. aui port disable si data: 00101111 so data: none the aui port will be disabled upon receiving this com- mand. subsequently, the imr+ chip will ignore all inputs (carrier sense and sqe) appearing at the aui port and will not transmit any data or jam sequence on the aui port. issuing this command will also cause the aui port to have its internal partitioning state machine forced to its idle state. therefore, a partitioned port may be re- connected by first disabling and then re-enabling the port.
amd preliminary 1 C 87 AM79C981 aui port enable si data: 00111111 so data: none this command enables a previously disabled aui port. note that a partitioned aui port may be reconnected by first disabling (aui port disable command) and then re- enabling the port with this command. all ports are enabled upon reset. tp port disable si data: 00100### so data: none (### is tp port number) the tp port designated in the command byte will be dis- abled upon receiving this command. subsequently, the imr+ device will ignore all inputs appearing at the dis- abled ports receive pins and will not transmit any data or jam sequence on that ports transmit pins. issuing this command will also cause a tp port to have its partition- ing state machine returned to its idle state (port recon- nected). therefore, a partitioned port may be reconnected by first disabling and then re-enabling the port. the disabled port will continue to report correct link test status. tp port enable si data: 00110### so data: none (### is tp port number) this command enables a previously disabled tp port. re-enabling a disabled port causes the port to be placed into link test fail state. this ensures that packet frag- ments received on the port are not repeated to the rest of the network. note that to force a tp port into the link fail state and/or to reconnect a partitioned tp port, the port should first be disabled (tp port disable command) and then re-enabled with this command. all ports are enabled upon reset. disable link test function of a tp port si data: 01000### so data: none (### is tp port number) this command disables the link test function at the tp port designated in the command byte, i.e., the tp port will no longer be disconnected due to link fail. a tp port which has its link test function disabled will continue to transmit link test pulses. if a twisted pair port has link test disabled, then reading the link test status indi- cates it being in link test pass. enable link test function of a tp port si data: 01010### so data: none (### is tp port number) this command re-enables the link test function in the tp port designated in the command byte. this com- mand executes only if the designated tp port has had the link test function disabled by the disable link test function command. otherwise, the command is ig- nored. link test is enabled upon reset. disable automatic receiver polarity reversal si data: 01100### so data: none (### is tp port number) this command disables the automatic receiver polarity reversal function for the tp port designated in the command byte. if this function is disabled on a tp port with reverse polarity (due to a wiring error), then the tp port will fail link test due to the reversed polarity of the link pulses. if the link test function is also disabled on the tp port, then the received reversed polarity packets would be repeated to all other network ports in the imr+ chip as inverted data. automatic polarity reversal is dis- abled upon reset. enable automatic receiver polarity reversal si data: 01110### so data: none (### is tp port number) this command enables the automatic receiver polarity reversal function for the tp port designated in the command byte. if enabled in a tp port, the imr+ chip will automatically invert the polarity of that tp ports re- ceiver circuitry if the tp port is detected as having reversed polarity (due to a wiring error). after reversing the receiver polarity, the tp port could then receive sub- sequent (reverse polarity) packets correctly. get (read) opcodes aui port status si data: 10001111 so data: pbsl0000 the combined aui status allows a single instruction to be used for monitoring aui port. the four status bits re- ported are:
amd preliminary 1 C 88 AM79C981 p partitioning status. this bit is 0 if the aui port is partitioned and 1 if connected. b bit rate error. this bit is set to 1 if there has been an instance of fifo overflow or underflow, caused by data received at the aui port. this bit is cleared when the status is read. s sqe test status. this bit is set to 1 if sqe test is detected by the imr+ chip. this bit is cleared when the status is read. a mau attached to a re- peater must have sqe test disabled. this bit is set even if the aui port is disabled or partitioned. l loop back error. the mau attached to the aui is required to loopback data transmitted to do onto the di circuit. if loopback carrier is not detected by the imr+ device, then this bit is set to 1 to report this condition. this bit is cleared when the status is read. for a repeater this is the only indication of a broken or missing mau. alternate aui port status si data: 10001111 so data: pbsl0000 there are three further variations of the above com- mand, allowing selective clearing of a combination of b, s, and l bits. they are primarily included for use by the himib chip. these are: alternative 1. si data: 10001011 so data: pbsl0000 b is not cleared. s and l are cleared. alternative 2. si data: 10001101 so data: pbsl0000 s and l are not cleared. b is cleared. alternative 3. si data: 10001001 so data: pbsl0000 none of s, b and l are cleared. tp port partitioning status si data: 10000000 so data: p7.................p0 pn = 0 tp port n partitioned pn = 1 tp port n connected the partitioning status of all eight tp ports are ac- cessed by this command. if a port is disabled, reading it partitioning status will indicate that it is connected. bit rate error status of tp ports si data: 10100000 so data: e7...............e0 this allows a single command to be used to report bit rate error condition (fifo overflow or underflow) of all twisted pair ports. the 8 bits of the output pattern corre- spond to each of the 8 tp ports, with least significant bit corresponding to port 0. the status bit for a port is set to 1 if there has been an instance when data received from that port has caused a fifo error. all status bits stay set until the status is read. link test status of tp ports si data: 11010000 so data: l7...............l0 ln = 0 tp port n in link test fail ln = 1 tp port n in link test pass the link test status of all eight tp ports are accessed by this command. a disabled port continues to report correct link test status. re-enabling a disabled port causes the port to be placed into link test fail state. this ensures that packet fragments received on the port are not repeated to the rest of the network. receive polarity status of tp ports si data: 11100000 so data: p7...............p0 pn = 0 tp port n polarity correct pn = 1 tp port n polarity reversed the statuses of all eight tp port polarities are accessed with this command. the imr+ chip has the ability to de- tect and correct reversed polarity on the tp ports rxd+/C pins. if the polarity is detected as reversed for a tp port, then the imr+ chip will set the appropriate bit in this commands result byte only if the polarity reversal function is enabled for that port. mjlp status si data: 11110000 so data: m00000000 each imr+ chip contains an independent mau jabber lock up protection timer. the timer is designed to in- hibit the imr+ device transmit function, if it has been transmitting continuously for more than 65536 bit times. the mjlp status bit (m) is set to 1 if this happens. this bit remains set and is only cleared when the mjlp status is read by using this command.
amd preliminary 1 C 89 AM79C981 version si data: 11111111 so data: xxxx0001 this command (1111 1111) can be used to determine the device version. the imr+ chip responds by the bit pattern : xxxx 0001 the imr chip (am79c980) responds by the bit pattern: xxxx 0000 minimum mode the minimum mode reconfigures the imr+ device management port and is intended to provide support for the low end, non-managed repeaters, requiring minimal external logic to provide led indication of: n twisted pair ports link status indication and aui loopback status n port partitioning status n twisted pair ports receiver polarity status and aui sqe test error status n port bit rate error status the minimum mode is selected by controlling the state of the test pin while rst is asserted. if test is high (asserted), while reset is active ( rst low), then mini- mum mode is selected. the state of si pin, at the deassertion of the rst signal, determines whether the imr+ chip is to be programmed for automatic polarity detection/correction. when entering the minimum mode, the test input has to be deasserted on the rising edge of reset. a maximum delay of 100 ns is allowed to account for slow devices. the following table summarizes the different modes available. test si functions 0 0 normal management mode 0 1 normal management mode 1 0 minimum mode, receive polarity correction disabled 1 1 minimum mode, receive polarity correction enabled in minimum mode, the so pin is used to serially output the various status information based on the state of the si and sclk pins. a summary of the status information is provided in the following table. sclk si so output 0 0 tp ports receive polarity status + aui sqe test error status. 0 1 bit rate error (all ports). 1 0 tp ports link status + aui loopbac k status 1 1 port partitioning status (all ports) when si = 0 then so will output the related aui status bits (loopback or sqe), followed by the 8 tp status bits (link or polarity), starting with the tp port 0. when si = 1, the port partitioning status or port bit rate error status are scanned out with the aui first and tp ports following. tp port 0 is scanned out first. note that the bit rate error, aui loopback, and aui sqe test error status bits stay set until they are scanned out. the state of si and sclk inputs is checked at the end of every str cycle. the rising edge of the x1 clock, occur- ring before falling edge of str, is used to strobe in the state of the si and sclk pins. in this minimum mode, the management port mode is not active. to exit the minimum mode, the imr+ device must reset into the normal management port mode.
amd preliminary 1 C 90 AM79C981 AM79C981 imr+ chip xtal osc ck d q async reset x1 x2 rst str so clr ck q q d 1/2 74 tck ck si sipo ck t p 7 t p 6 t p 5 t p 0 a u i 1/2 74 tck sclk si 17306b-7 register test figure 3. minimum mode, non-intelligent repeater example x1 crs (note 2) str crs aui crs tp0 crs tp1 crs tp2 crs tp3 crs tp4 crs tp5 crs tp6 crs tp7 crs aui tck (note 1) so (note 3) so aui so tp0 so tp1 so tp2 so tp3 so tp4 so tp5 so tp6 so tp7 so aui 17306b-8 notes: 1. externally generated signal illustrates internal imr+ chip clock phase relationship. 2. crs timing with the c-bit cleared (imr+ chip programmable options) 3. for minimum hub mode figure 4. management port minimum mode and port activity monitor signal relationship port activity monitor two pins, crs and str, are used to serially output the state of the internal carrier sense signals from the aui and the eight tp ports. this function together with exter- nal hardware and/or software can be used to monitor re- peater receive and/or collision activity. the following diagram shows typical external hardware employed to convert the serial bit stream into parallel form. the accuracy of the crs signals is 10 bit times (bt) (1 m s). specifically, a transition to active state by any of the internal carrier sense bits that lasts for less than 10bt is latched internally and is used to set the ap- propriate bit during the next sample period.
amd preliminary 1 C 91 AM79C981 AM79C981 imr+ chip xtal osc ck d q async reset x1 x2 rst str crs clr ck q q d 1/2 74 tck ck si sipo ck register t p 7 t p 6 t p 5 t p 0 a u i shift register carrier sense outputs 1/2 74 tck 17306b-9 figure 5a. port activity monitor implementation 17306b-10 rst x1 tck (not e 1) crs str (note 3) 12 9 1 0 1 1 aui tp0 tp1 tp7 x aui tp0 (note 2) notes: 1. externally generated signal illustrates internal imr+ chip clock phase relationship. 2. imr+ chip standalone, x will be low. when attached to a himib device, x reflects the state of the ci pair. 3. str signal is not available when the imr+ chip is attached to himib device, and must be generated externally. figure 5b. port activity monitor implementation (continued)
amd preliminary 1 C 92 AM79C981 loopback test mode the imr+ chip can be programmed to enter loopback mode on all network ports. this is accomplished by first driving the test pin high, then clocking (using the sclk pin) a minimum of three 0s into the si pin. this causes the imr+ chip to loop all received data on each port back to each ports corresponding transmit outputs. specifically, the aui di input is passed unaltered to the aui do output, and each rxd input on the twisted pair ports is passed (unaltered) to the respective txd and txp outputs. only receive data that passes the required amplitude squelch criteria is looped back to the transmit outputs. note that the data is looped back unaltered, meaning that no signal retiming or regeneration takes place. therefore, any signal distortion present on the re- ceive data paths will be retransmitted. in minimum mode, the loopback test mode cannot be accessed. the imr+ device will return to normal opera- tion when the test pin is again driven low. test si sclk 17306b-11 figure 6. programming the imr+ device for loopback mode
amd preliminary 1 C 93 AM79C981 imr+ chip external components figure 6 shows a typical twisted pair port external com- ponents schematic. the resistors used should have a 1% tolerance to ensure interoperability with 10base-t compliant networks. the filters and pulse transformers are necessary devices that have a major influence on the performance and compliance of the 10base-t ports of the repeater. specifically, the transmitted waveforms are heavily influenced by the filter characteristics and the twisted pair receivers employ several criteria to con- tinuously monitor the incoming signals amplitude and timing characteristics to determine when and if to assert the internal carrier sense. for these reasons, it is crucial that the values and tolerances of the external compo- nents be as specified. several manufacturers produce a module that combines the functions of the transmit and receive filters and the pulse transformers into one package. notes: 1. compatible filter modules, with a brief description of package type and features are included in the appendix. 2. the resistor values are recommended for general purpose use and should allow compliance to the 10base-t specification for template fit and jitter performance. however, the overall performance of the transmitter is also affected by the transmit filter configuration. 17306b-12 1.21k w 100 w 61.9 w 422 w xmt filter rcv filter filter & transformer module note 1 note 2 txp+ txdC txpC txd+ rxd+ rxdC 61.9 w 422 w rj45 connector td+ tdC rd+ rdC 3 6 1 2 1:1 1:1 AM79C981 figure 7a. typical tp port external components 17306b-13 doC di+ diC ci+ ciC do+ pulse transformer note 1 40.2 w optional anlg gnd 0.1 m f 0.1 m f aui connector 40.2 w 40.2 w 40.2 w 3 10 5 12 2 9 AM79C981 notes: 1. compatible aui transformer modules, with a brief description of package type and features are included in the appendix. 2. the differential input di and the ci pairs are externally terminated by two 40.2 w 1% resistors and one optional common- mode bypass capacitor. the differential input impedance, zidf, and the common-mode input impedance, zicm, are speci- fied so that the ethernet specification for cable termination impedance is met using standard 1% resistor terminators. if sip devices are used, 39 w is the nearest usable equivalent value. figure 7b. typical aui port components
amd preliminary 1 C 94 AM79C981 applications a fully managed multiport repeater can be easily built by interfacing the imr+ chip with the hardware imple- mented management information base (himib), am79c987 device. the himib device interfaces with all common microprocessor system busses with a minimum of external logic. note that additional buffering of dat and jam are required for most applications. for more information, refer to amds ieee 802.3 repeater technical manual (pid# 17314a). 17306b-14 himib imr+ crs str si so sclk crs str si so sclk req dat jam ack col rst ck address decode cs c/ d data buffer rd wr rdy host system bus expansion bus d [7C0] x 1 int figure 8. simplified isa-hub block diagram
amd preliminary 1 C 95 AM79C981 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature under bia s 0 to 70 c . . . . . . . supply voltage referenced to av ss or dv ss (av dd , dv dd ) C0.3 to +6 v . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a ) 0 to +7 0 c . . . . . . . . . . . . . . . . supply voltage (av dd , dv dd ) 5 v to 5 % . . . . . . . operating ranges define those limits between which the fun- tionality of the device is guaranteed . dc characteristics over operating ranges unless otherwise specified parameter symbol parameter description tes t conditions min max unit digital i/o v il input low voltage dv ss = 0.0 v C0.5 0.8 v v ih input high voltage 2.0 dv dd +0.5 v v ol output low voltage i ol = 4.0 ma C 0.4 v v oh output high voltage i oh = C0.4 ma 2.4 C v i il input leakage current dv ss amd preliminary 1 C 96 AM79C981 dc characteristics (continued) parameter symbol parameter description tes t conditions min max unit twisted pair ports i irxd input current at rxd+/- av ss amd preliminary 1 C 97 AM79C981 switching characteristics over operating ranges unless otherwise specified parameter symbol parameter description tes t conditions min max unit clock and reset t x1 x1 clock period 49.995 50.005 ns t x1h x1 clock high 20 30 ns t x1l x1 clock low 20 30 ns t x1r x1 clock rise time C 1 0 n s t x1f x1 clock fall time C 1 0 n s t prst reset pulse width after power on 150 C m s ( rst pin low) t rst reset pulse width 4 C m s ( rst pin low) t rstset rst high setup time wit h 20 C n s respect to x1 clock t rsthld rst low hold time with 0 C ns respect to x1 clock management port t sclk sclk clock period 100 C n s t sclkh sclk clock high 30 C n s t sclkl sclk clock low 30 C n s t sclkr sclk clock rise time C 1 0 n s t sclkf sclk clock fall time C 1 0 n s t siset si input setup time with respect to scl k 10 C n s rising edge t sihld si input hold time with 10 C n s respect to sclk rising edge t sodly so output delay wit h c l = 100 pf C 40 ns respect to sclk rising edge t x1hcrs x1 rising edge to crs valid c l = 100 pf 5 40 ns t x1hsth x1 rising edge to str hig h c l = 100 pf C 40 ns t x1hstl x1 rising edge to str lo w c l = 100 pf C 40 ns t testset test input setup time with respect t o 10 C n s sclk rising edge t testhld test input hold time with respect t o 10 C n s sclk rising edge t strset str setup time 5 C ns t strhld str hold time 12 C n s expansion port t x1hrl x1 rising edge to req driven lo w c l = 100 pf 14 40 ns t x1hrh x1 rising edge to req driven hig h c l = 100 pf 14 40 ns t x1hdr x1 rising edge to dat/jam drive n c l = 100 pf 14 40 ns t x1hdz x1 rising edge to dat/jam not driven c l = 100 p f 14 40 ns
amd preliminary 1 C 98 AM79C981 switching characteristics (continued) parameter symbol parameter description tes t conditions min max unit expansion port (continued) t djset dat/jam setup time 10 C n s t djhold dat/jam hold time 14 C n s t caset col / ack setup time 5 C ns t cahold col / ack hold time 14 C n s t mhset test setup time with respect to rst 200 C n s to enter minimum hub mode t mhhld test hold time with respect to rst 0 100 ns to enter minimum hub mode t sclkset si, sclk set up time with respect to x1 50 C n s t sclkhld si, sclk hold time with respect to x1 50 C n s aui port t dotd x1 rising edge to do toggle C 3 0 n s t dotr do+,do- rise time (10% to 90%) 2.5 5.0 ns t dotf do+,do- fall time (90% to 10%) 2.5 5.0 ns t dorm do+,do- rise and fall time mismatch C 1.0 ns t doetd do+/- end of transmission 275 375 ns t pwodi di pulse width accept/reject |v in | > |v asq | 1 5 4 5 n s threshold (note 3) t pwkdi di pulse width maintain/turn-off |v in | > |v asq | 136 200 ns threshold (note 4) t pwoci ci pulse width accept/reject |v in | > |v asq | 1 0 2 6 n s threshold (note 5) t pwkci ci pulse width maintain/turn-off |v in | > |v asq | 9 0 160 ns threshold (note 6) twisted pair ports t txtd x1 rising edge to txd+,txp+ C 5 0 n s txd-,txp- transition delay t tr txd+,txd-,txp+,txp- rise time C 2 0 n s t tf txd+,txd-,txp+,txp- fall time C 2 0 n s t tm txd+,txd-,txp+,txp- rise C 6 ns and fall time mismatch t tetd transmit end of transmission 275 375 ns t pwkrd rxd pulse width maintain/turn-off |v in | > |v ths | 130 200 ns threshold (note 7) t perlp idle signal period 8 2 4 m s t pwlp idle link test pulse width (txd+) 75 120 ns t pwplp idle link test pulse width (txp+,txp-) 40 60 ns
amd preliminary 1 C 99 AM79C981 switching characteristics (continued) notes: 1. parameter not tested. 2. uses switching test load. 3. di pulses narrower than t pwodi (min) will be rejected; pulses wider than t pwodi (max) will turn internal di carrier sense on. 4. di pulses narrower than t pwkdi (min) will maintain internal di carrier sense on; pulses wider than t pwkdi (max) will turn internal di carrier sense off. 5. ci pulses narrower than t pwoci (min) will be rejected; pulses wider than t pwoci (max) will turn internal ci carrier sense on. 6. ci pulses narrower than t pwkci (min) will maintain internal ci carrier sense on; pulses wider than t pwkci (max) will turn internal ci carrier sense off. 7. rxd pulses narrower than t pwkrd (min) will maintain internal rxd carrier sense on; pulse wider than t pwkrd (max) will turn internal rxd carrier sense off. 8. for the typical twisted pair load as shown in figure 7, using a 100 w cable, an additional 28 ma (max) of i dd current is required for each twisted pair port used. less than 18% of the power associated with this additional current is dissipated by the imr+ chip; the remainder is dissipated externally in the twisted pair load and cable.
amd preliminary 1 C 1 00 AM79C981 key to switching waveforms must be steady may change from h to l may change from l to h does not apply dont care any change permitted will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high impedance off state waveform inputs outputs ks000010 switching waveforms t x1 t x1h t x1l t x1r t x1f x1 17306b-15 clock timing
amd preliminary 1 C 1 01 AM79C981 switching waveforms t rst or t prst x1 rst t rstset notes: t rstset refers to synchronous reset timing. *externally generated (figure 4) signal illustrates internal imr+ device clock phase relationships. t rsthld tck* 17306b-16 reset timing t siset t sodly t sclk t sclkf t sclkr sclk si/test so t sodly t sihld t sclkh t sclkl t testset t testhld 17306b-19 management port clock timing
amd preliminary 1 C102 AM79C981 switching waveforms x1 req ack col dat jam in t djset t djhold tck* 17306b-20 note: *externally generated (figure 4) signal illustrates internal imr+ chip clock phase relationships. expansion port input timing x1 req ack col dat jam out t x1hdr t x1hdz t x1hrl t x1hrh t caset t cahold t caset tck* 17306b-21 note: *externally generated (figure 4) signal illustrates internal imr+ chip clock phase relationships. expansion port output timing
amd preliminary 1 C 1 03 AM79C981 switching waveforms x1 req ack col t x1hrl t x1hrh t caset t cahold t caset in in tck* dat jam 17306b-22 note: *externally generated (figure 4) signal illustrates internal imr+ chip clock phase relationships. expansion port collision timing test t mhset t mhhld rst 17306b-23 to enter minimum mode x1 str si, sclk t x1hsth t x1hstl dont care t sclkset t sclkhld 17306b-24 dont care minimum mode
amd preliminary 1 C 1 04 AM79C981 switching waveforms x1 d0+ d0C 1 t dotd t dotr t dotf t doetd 0111010 e t d 17306b-25 aui do timing diagram t doetd do+/C 40 mv 100 mv max. 0 v 80-bit times 17306b-26 aui port do etd waveform di+/C v asq t pwodi t pwkdi t pwkdi 17306b-27 aui receive timing diagram
amd preliminary 1 C105 AM79C981 switching waveforms ci+/C v asq t pwoci t pwkci t pwkci 17306b-28 aui collision timing diagram x1 txd+ txp+ 1 011101 0 e t d txdC txpC 0 1 t txetd t txtr t txtd t xtxtf t txtd 17306b-29 tp ports output timing diagram
amd preliminary 1 C 1 06 AM79C981 switching waveforms t pwplp t pwlp t perlp txd+ txp+ txdC txpC t pwplp 17306b-30 tp idle link test pulse rxd+/C t pwkrd v ths+ v thsC t pwkrd v tsq+ v tsqC t pwkrd 17306b-31 tp receive timing diagram
amd preliminary 1 C 1 0 7 AM79C981 switching test circuits av dd do+ 154 w 100 pf doC av ss 52. 3 w test point 17306b-32 includes test jig capacitance aui do switching test circuit dv dd txd+ 294 w 100 pf txdC dv ss 29 4 w test point includes test jig capacitance 17306b-33 txd switching test circuit dv dd txp+ 71 5 w 100 pf txpC dv ss 71 5 w test point includes test jig capacitance 17306b-34 txp outputs test circuit
appendix 1-108 AM79C981 a 10base-t interface the table below lists the recommended resistor values and ?lter and transformer modules for the imr+ device. imr+ device compatible 10base-t media interface modules ? manufacturer part # package description bel fuse s556-5999-32 16-pin smd transmit and receive ?lters, transformers and common mode chokes. bel fuse 0556-2006-14 10-pin sil transmit and receive ?lters, transformers and common mode chokes. bel fuse a556-2006-de 16-pin 0.3" dil transmit and receive ?lters and transformers. bel fuse a556-2006-00 16-pin dil transmit ?lter, transformers and common mode choke. receive ?lter and transformer. halo electronics fs02-101y4 "slim sip" transmit and receive ?lters and transformers. halo electronics fs12-101y4 "slim sip" transmit and receive ?lters and transformers, transmit common mode reduction choke. halo electronics fs22-101y4 "slim sip" transmit and receive ?lters, transformers and common mode chokes. halo electronics fd02-101g 16-pin 0.3" dil transmit and receive ?lters and transformers. halo electronics fd12-101g 16-pin 0.3" dil transmit and receive ?lters and transformers, transmit common mode choke. halo electronics fd22-101g 16-pin 0.3" dil transmit and receive ?lters, transformers and common mode chokes. halo electronics fd22-101r2 16-pin 0.3" dil termination and equalization resistors, transmit and receive ?lters, transformers and common mode chokes. nano pulse 5408-37 16-pin smd 7 pole transmit and receive ?lters with 1ct:1ct xfmrs (transmit & receive) and a separate common mode choke for each channel. nano pulse 5408-40 9-pin sip 7 pole transmit and receive ?lters with 1ct:1ct xfmrs (transmit & receive) and a separate common mode choke for each channel. nano pulse 6612-21 12-pin dil 7 pole transmit and receive ?lters with 1ct:1ct xfmrs (transmit & receive) and a separate common mode choke for each channel. pca electronics epa1990a 16-pin 0.3" dil transmit and receive ?lters and transformers. pca electronics epa1990ag smt device transmit and receive ?lters and transformers. pca electronics epa2013d 16-pin 0.3" dil transmit and receive ?lters and transformers, transmit common mode choke. pca electronics epa2013dg smt device transmit and receive ?lters and transformers, transmit common mode choke. pulse engineering 78z034c 16-pin dil transmit and receive ?lters and transformers, transmit common mode chokes. pulse engineering 78z1120b-01 16-pin dil transmit and receive ?lters and transformers. pulse engineering 78z1122b-01 16-pin dil transmit and receive ?lters, transformers and common mode chokes. pulse engineering pe-68017s 10-pin sil transmit and receive ?lters, transformers and common mode chokes. pulse engineering pe-68026 16-pin smt transmit and receive ?lters, transformers and common mode chokes. pulse engineering pe-68056 16-pin smt transmit and receive ?lters, transformers and common mode chokes. pulse engineering pe-68032 13-pin pcmcia-smt transmit and receive ?lters and transformers, transmit common mode chokes. tdk tla-3m601-rs 10-pin sip transmit and receive ?lters and transformers, transmit common mode chokes. tdk tla-3m102(-t) 16-pin smd integrated resistors, transmit and receive ?lters and transformers, transmit common mode chokes. tdk tla-3m103(-t) 16-pin smd transmit and receive ?lters and transformers, transmit common mode chokes. valor electronics pt3877 16-pin 0.3" dil transmit and receive ?lters and transformers. valor electronics pt3983 8-pin 0.3" dil transmit and receive common mode chokes. valor electronics fl1012 16-pin 0.3" dil transmit and receive ?lters and transformers, transmit common mode chokes.
3 AM79C981 1 C 1 09 glossary appendix b active status in a non-collision state, an imr+ chip is considered ac- tive if it is receiving data on any one of its network ports, or is in the process of broadcasting (repeating) fifo data from a recently completed data reception. in a colli- sion state (the imr+ device is generating jam se- quence), an imr+ device is considered active if any one or more network ports is receiving data. the imr+ de- vice asserts the req line to indicate that it is active. collision in a carrier sense multiple access/collision detection (csma/cd) network such as ethernet, only one node can successfully transfer data at any one time. when two or more separate nodes (dtes or repeaters) are si- multaneously transmitting data onto the network, a col- lision state exists. in a repeater using one or more imr+ devices, a collision state exists when more than one network port is receiving data at any instant, or when any one or more network ports receives data while the imr+ device is transmitting (repeating) data, or when the ci+/- pins become active (nominal 10 mhz signal) on the aui port. jam sequence a signal consisting of alternating 1s and 0s that is gener- ated by the imr+ device when a collision state is de- tected. this signal is transmitted by the imr+ device to indicate to the network that one or more network ports in the repeater is involved in a collision. network port any of the eight 10base-t ports or the aui port present in the imr+ device (i.e. not the expansion port or the management port). partitioning a network port on a repeater has been partitioned if the repeater has internally disconnected it from the repeat- er due to localized faults that would otherwise bring the entire network down. these faults are generally cable shorts and opens that tend to cause excessive collisions at the network ports. the partitioned network port will be internally re-connected if the network port starts behav- ing correctly again, usually when successful collision- less transmissions and/or receptions resume. receive collision a network port is in a receive collision state when it de- tects collision and is not one of the colliding network nodes. this applies mainly to a non-transmitting aui port because a remote collision is clearly identified by the presence of a nominal 10 mhz signal on the ci+/- pins. however, any repeater port would be considered to be in a receive collision state if the repeater unit is re- ceiving data from that port as the one-port-left in the collision sequence. transmit collision a network port is in a transmit collision state when colli- sion occurs while that port is transmitting. on the aui port, transmit collision is indicated by the presence of a nominal 10 mhz signal on the ci+/- pins while the aui port is transmitting on the do+/- pins. on a 10base-t port, transmit collision occurs when incoming data ap- pears on the rxd+/- pins while the 10base-t port is transmitting on the txd+/- and txp+/- pins.
1-1 10 AM79C981

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